0.7 Nanometer: IBM shows the first chips with CFET transistors

▤ Summary

IBM unveiled a new chip manufacturing concept aimed at the 0.7-nanometer class, based on stacked complementary transistors called CFETs. The design promises higher transistor density, better performance, lower power consumption, and a smaller SRAM cache footprint than IBM’s earlier 2-nm process. IBM uses wafer bonding and separate optimization for NMOS and PMOS layers to improve density, even though the approach adds fabrication complexity and cost. The company expects the nanostack approach to become suitable for volume production around 2031, with partners such as Tokyo Electron, Lam Research, and Screen Semiconductor Solutions involved in the development.

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