Siemens integrated circuit test and analysis at 5nm and below
Summary
As IC designs progress to more advanced nodes at 5nm and below, they become increasingly susceptible to manufacturing variations that can create defects and slow yield ramp. "Tessent Hi-Res Chain represents a major leap forward in our ability to rapidly identify and address yield-limiting factors in advanced IC designs," said Ankur Gupta, vice president and general manager of the Digital Design Creation Platform division, Siemens Digital Industries Software. "By providing unprecedented accuracy and resolution in defect isolation, were empowering our customers to accelerate their yield ramp and improve time-to-market for cutting-edge semiconductor products." This high level of reliability has made Tessent the go-to solution for yield ramping across multiple technology nodes. These tools work in concert to provide the highest test coverage, accelerate yield ramp, and improve quality and reliability throughout the silicon lifecycle.
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