Xcelium Parallel Logic Simulation

▤ Summary

Its unique compile/elaboration process analyzes each design’s dependency graph and automatically maps it to the optimal number of cores to maximize its speed. Users can set the number of cores on the command line without recompile. The Xcelium simulator further extends innovation within the Cadence Verification Suite, which is comprised of best-in-class core engines, verification fabric technologies, and solutions that increase design quality and throughput, thus fulfilling verification requirements for a wide variety of use cases and vertical segments.

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