Free reference model riscvOVPsimPlus updated
Summary
The P (or Packed SIMD/DSP) extension is a significant addition to the flexibility of the modular RISC-V ISA (Instruction Set Architecture); it supports real-time data processing applications as part of the main processor pipeline without the need for the associated inefficiencies of a co-processor. riscvOVPsimPlus is a popular free ISS (Instruction Set Simulator) that is an envelope model that can be configured to cover all of the ratified RISC-V specifications and standard extensions. The currently released test suites available free on the OVP website now include P‑SIMD/DSP, K-crypto, V-vector, B-bitmanip, F, D, I, M, and C. “Flexibility within a framework of compatibility is the essential foundation of the RISC-V ISA,” said Chuanhua Chang, Andes Technology, Chair of RISC-V International P Extension Task Group. However, the hardware specification is just the start - adoption and success depend on the software ecosystem, which is supported with the reference models and test suites from Imperas.” “By combining SIMD/DSP functionality within the RISC-V ISA offers the ideal balance for performance, flexibility and efficiency,” said Wei Wu, PLCT Lab, ISCAS, Vice-Chair of RISC-V International P Extension Task Group. The adoption of riscvOVPsimPlus with the new RISC-V P extension support helps provide clarification of the specification boundary as a useful guideline for innovation in new processor designs.”