IP for PCI Express 5.0 specification on TSMC N5 process
Summary
With Cadence’s PHY and Controller Subsystem for PCIe 5.0 architecture, customers can design extremely power-efficient SoCs with accelerated time to market. The Cadence IP for PCIe 5.0 architecture offers a highly power-efficient implementation of the standard, with several evaluations from customers indicating it provides industry power at the maximum data transfer rate of 32GT/s and worst-case insertion loss. In conjunction with Cadence’s low-latency Controller IP for Compute Express Link (CXL), the Cadence PHY IP for PCIe 5.0 technology enables a new class of applications for cache-coherent interconnects for processors, workload accelerators and memory expanders, as well as support for a wide range of Ethernet protocols. “Our close collaboration with Cadence will help our mutual customers meet the stringent power and performance requirements and accelerate silicon innovation with leading-edge design solutions benefiting from TSMC’s advanced technologies.” “Increasingly, our customers are demanding not just point IP, but total solutions that provide an edge by shortening development timeline and accelerating end-product deployment. Developing a solution with such low power for PCIe 5.0 architecture is a testament to the innovation our engineering teams can bring to bear to support our high-performance customer base.” “Cadence’s PHY and controller test chips for PCIe 5.0 showed robust performance in compliance tests on our Xgig exerciser and analyser platform,” said Tom Fawcett, Vice President and General Manager, Lab & Production Business Unit, VIAVI Solutions.