The UP Squared Chronicles Episode 4: Using Intel Processor Trace with POST Codes
Summary
Alternatively, and for the purposes of this article, the POST code is output from the serial port while a debug image that I built for the UP Squared board boots. Using our powerful macro language, you set a breakpoint at port 80 writes, run until you hit it, and then display the contents of the AX register (the POST code) all by concatenating three commands on one line of the Command CLI window: And, if you’re really clever, you set up Intel Processor Trace to trigger on these breakpoints, and capture a ton of instruction execution trace leading up to the OUT instruction. And scanning through the build directory, we find that this text string comes from PciLib.c, within function PciHostBridgeEnumerator(): Using Intel Processor Trace can yield us this insight, as to how post codes are handled. And you can make it bigger, of course, based upon how much system memory you have; it just makes it slower based upon the amount of trace data you’re collecting) and, by also expanding the scale from x1 to x64 to zero in on the code area of interest, can now see the flow back to PciHostBridgeEnumerator(): The ReportDispatcher() code is to the right of the Trace discontinuity white gap (callback function) and the PCI routines about to do the heavy lifting are to the left. When I did a “Go” on the target and stopped at the next POST code, which happens to be x’95’, the PuTTY console displays the output of the device discovery: All of which makes sense!
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