OpenFive Enhances Differentiated IP Portfolio with Die-to-Die Interface Controllers for HPC and Chiplet Markets
Summary
OpenFive Die-to-Die IP is intended to enable SoC architects to connect chip logic to optimized XSR/VSR/SR based SerDes while embracing native customer-defined interfaces, or Arm® AMBA® AXI. “Additionally, working with our leading SerDes partners, we can offer a complete sub-system solution optimized for their needs.” OpenFive is uniquely positioned with over a decade of experience in providing solutions for leading networking, storage, and AI products with its Interlaken IP for Chip-to-Chip connectivity, coupled with 2.5D-based ASIC integration experience for HBM2E based products. OpenFive will continue to extend the series of Die-to-Die IP portfolio for other parallel PHY based architectures in the future as they become available. OpenFive is a self-contained and autonomous custom silicon business unit of SiFive and offers customizable and differentiated SoC IP for Artificial Intelligence, Edge Computing, HPC, and Networking solutions. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs.