VT-rp, HLAT, and my AAEON Alder Lake Core i7-1270PE board: Part 3
Summary
Author’s Note: in Part 2, I mistakenly observed that all P-cores had HLAT enabled once P9 entered the NT normal kernel, when the 12th VM Launch breakpoint was hit. And to see the pattern visually, here’s an update to the logical processor behavior as the target boots through 24 successive SourcePoint VM Launch breakpoints: The legend associated with this matrix bears some explanation: The rows display the status of each logical processor through successive VM Launch breaks, 1-24. The key addition to the previous matrix is that when a particular logical processor is enabled for HLAT, there’s a cross-hatching pattern in the cell. Given the above, it’s worthwhile staring at the matrix for a while; it provides a lot of insight into the Windows boot flow with Hyper-V enabled, and the pattern of HLAT initialization. I’ll highlight just a few points of interest: At the 10th VM Launch breakpoint, all P-cores are in the Windows VMM, and all E-cores are still in UEFI.
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