SignatureIP Networks-on-Chips to accelerate RISC-V designs
Summary
When we set out on initial product development in 2021, it was clear that the processor landscape was undergoing a fundamental shift, from industry-wide dependence on one main architecture to encompassing an open-source revolution. SignatureIP’s NoCs support industry-standard interfaces and protocols, ensuring seamless integration with other IP blocks and peripherals typically found in RISC-V based designs. Roger Espasa, CEO and Founder, of Semidynamics, a European supplier of RISC-V IP cores specialising in high-bandwidth, high-performance cores with vector units targeted at machine learning and artificial intelligence applications, says: “The close collaboration between members of the RISC-V community is one of the driving forces of the architecture’s rapidly growing adoption. By combining our technologies, customers can create multi-core chip designs on a fully coherent RISC-V/CHI platform and then prototype them on an FPGA to demonstrate the integrated performance.” According to Mike Eftimakis, VP Strategy and Ecosystem at Codasip, a specialist in RISC-V custom compute solutions: “At Codasip, we are focused on enabling designers to customise their solutions to significantly improve their PPA. By working together, we ensure the continued evolution and widespread adoption of RISC-V as a pivotal force in the future of computing.” Samuel Chiang, Deputy Director of Marketing at Andes Technology, a supplier of high-performance/low-power RISC-V processor IP, says: “SignatureIP’s NoC solutions, with a focus on interoperability and configurability, are entering the market at the right time.