Semiwise, sureCore, and Cadence CMOS circuit development breakthrough
Summary
This allowed us to create PDK-quality compact transistor models that include corners and mismatch," said Professor Asen Asenov, CEO of Semiwise. sureCore CEO Paul Wells said: “The critical storage element, the bit cell, must essentially be treated as an analog circuit that is very sensitive to process variability and mismatch. When we develop new memory designs and their associated compilers, we need to run thousands of statistical circuit simulations to guarantee the yield and reliability of our IP.” “We are excited to work with Semiwise and sureCore in developing models in the Spectre Simulation Platform for use on cryogenic CMOS circuits,” said Tom Beckley, Senior Vice President and General Manager, Custom IC & PCB Group, Cadence. “We are delighted that the Spectre Simulation Platform now has calibrated SPICE models for cryogenic environments.” The first 22FDX SRAM tapeout by sureCore to validate both recharacterised standard cells and a range of embedded memory IP in the framework of the Innovate UK CryoCMOS project, enabled by the modifications in Cadence’s Spectre Simulation, is scheduled for early 2024. With the ability to simulate everything from architectural exploration to final analog and mixed-signal full-chip verification, this platform delivers increased productivity and throughput.