New processor achieves remarkable speedup in problem solving
Summary
Annealing processors are designed specifically for addressing combinatorial optimisation problems, where the task is to find the best solution from a finite set of possibilities. In a new IEEE Access study published on 30 January 2024, led by Professor Takayuki Kawahara from Tokyo University of Science, researchers have developed and successfully tested a scalable processor that divides the calculation into multiple LSI chips. Using the unique processing architecture announced by the Tokyo University of Science in 2020, we have realised a fully coupled LSI (Large Scale Integration) on one chip using 28nm CMOS technology. In terms of power performance ratio, the processor outperformed simulating a fully coupled Ising system on a PC (i7, 3.6GHz) using annealing emulation by 2,306 times. The goal is to achieve this without the need for air conditioning, large equipment, or cloud infrastructure, using current semiconductor processes.