Imec debuts high-speed ADC, leads in efficiency
Summary
Imec’s massively time-interleaved slope-ADC design offers high power efficiency and a very compact footprint, while promising to enable exceptional conversion speeds. As such, when scaling to sampling rates far beyond 100GS/s, the SAR ADC approach results in a significant area increase and long interconnection lines, translating into substantial parasitics and energy loss. As a result, higher power efficiency and scalability can be achieved, while significantly reducing the ADC’s surface area,” said Joris Van Driessche, program manager at imec. And its benefits will only become more significant as we move to higher speeds (150GS/s and beyond).” In fact, a 5nm ADC using the same architecture is currently being completed – targeting sampling rates well above 150GS/s while achieving extremely low power consumption. Late last year, for example, imec researchers at Ghent University developed an optical receiver achieving a gross data rate of 200 Gbps by co-integrating a traveling-wave SiGe BiCMOS transimpedance amplifier with a silicon photonics Ge photodetector to combine the need for speed with a scalable and affordable implementation.