Avery Design Systems Announces SimRegress and SimCompare
Summary
Converters from the Avery database to Verdi FSDB and SimVision are supported to generate and inspect the waveforms. SimCompare correlates RTL and gate-level signal names and transaction synchronization between the two simulations being compared. The SimDiff application is integrated with Verdi and SimVision to directly scope these respective waveforms and source code debug tools and windows for more detailed inspection. Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers.