Cadence and Imperas support NSITEXE RISC V
Summary
ImperasDV is a RISC-V processor verification solution based on the industry-leading lock-step continuous compare methodology. It enables both the accurate detection of issues and the efficient resolution of discrepancies between the design under test and the Imperas RISC-V Reference Model. “As the NSITEXE Akaria processors are adopted across a wide range of next-generation automotive, safety-critical, and embedded applications, the verification methodology with the support from Imperas and Cadence has been invaluable in achieving our quality goals and on-time development schedule.” “By integrating our Xcelium Logic Simulator with Imperass RISC-V verification technology, weve empowered NSITEXE to design the next generation of its Akaria processors, which are optimised for safety-critical applications and compliant with the ISO 26262 ASIL D standard,” said Paul Cunningham, general manager of the System & Verification Group at Cadence. “Our work together exemplifies Cadence’s commitment to collaboration and innovation to support our customers in the rapidly evolving semiconductor industry.” “Processor verification is challenging, and yet critical to RISC-V adoption,” said Simon Davidmann, CEO at Imperas Software Ltd. “ImperasDV is the first commercially available RISC-V processor verification solution, and the achievement of the tight integration with Cadence is key to the successful use of ImperasDV by NSITEXE.” Cadence, Imperas, and NSITEXE have released more detail on the design flow and implementation of the lock-step continuous compare RISC-V verification methodology as a case study. The case study describes the integration between Imperas and Cadence tools used and details of the full verification flow.