Boundary Scan Description Language (BSDL) Explained
Summary
Having a good understanding of the BSDL leads to a deeper knowledge of JTAG, that in turn grants insight into the technology behind IEEE 1687, also known as IJTAG. In this article, I’ll provide a tutorial and practical description of the BSDL, and how it is used as a platform all of the test, validation, debug, and programming applications, on chips and boards, that JTAG and IJTAG enable. In the interest of brevity, in this article, I’ll focus on the main statements that provide insight into the inner JTAG workings of ICs, and restrict coverage to the most widely deployed version of boundary scan, IEEE 1149.-2001. entity refers to the Spartan 6 FPGA; in this case, XC6SLX9_FTG256. The INSTRUCTION_CAPTURE attribute is kind of subtle; it denotes the bit pattern that is loaded into the instruction register when the TAP controller passes through the Capture-IR state. As the Spartan 6 contains 612 cells, I’ll just excerpt an early part of the BSR description here: The BOUNDARY_LENGTH attribute specifies the length of the boundary register, as you might expect.
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