Avalanche Technology Presents Solutions for Satellite Mission Adaptability at the SEE-MAPLD Workshop
Summary
Paul Chopelas, Avalanche General Manager, is honored to present solutions enabling satellite mission adaptability at the upcoming Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop. SEE MAPLD brings together academic, government and commercial interests to examine the latest research and the newest microelectronics technologies available to bolster resilience, capability and adaptability of aerospace and defense systems, primarily for space environments. Specifically, combining all three, Avalanche Technology’s MRAM-based boot module solutions now allow the use of Firmware Over-The-Air (FOTA) updates and multiple code images for advanced AMD/Xilinx adaptive SoC platforms used in space-based applications such as Versal and UltraScale. Leveraging disruptive Gen 3 Space Grade Dual QSPI Persistent SRAM (P-SRAM™) family with its robust, yet flexible write protection schemes, industry leading endurance (10^16) and pin compatible density options shipping today from 1Gb to 8Gb, these advanced satellite architectures can now mirror the simplicity of terrestrial systems. I look forward to exchanging learnings and new ideas with the community at SEE MAPLD.” The Gen 3 Space Grade families are offered as a standard product in Parallel with asynchronous SRAM-compatible timing and Dual QSPI high speed serial interface in various density options from 1Gb to 8Gb.
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