Microchip unveils terabit-scale secure ethernet PHY family with port aggregation
Summary
These are the first to integrate 1.6Tbp/s (terabits per second) of line-rate end-to-end encryption and port aggregation to maintain the most compact footprint in the transition to 112Gb PAM4 connectivity for enterprise ethernet switches, security appliances, cloud interconnect routers and optical transport systems. “By offering both hardware and software footprint compatibility, our customers can leverage architectural designs across their enterprise, datacentre, and service provider switching and routing systems that can offer pay-as-you-need enablement of advanced features including end-to-end security, multi-rate port aggregation, and precision timestamping via software subscription model.” META-DX2+’s configurable 1.6Tbp/s datapath architecture outperforms the next near competitors by 2x in total gearbox capacity and hitless 2:1 protection switch mux modes enabled by its ShiftIO capability. Also, the devices include IEEE 1588 Class C/D Precision Time Protocol (PTP) support for accurate nanosecond timestamping required for 5G and enterprise business critical services. • Integrated 1.6T MACsec/IPsec engines that offload encryption from packet processors so systems can more easily scale up to higher bandwidths with end-to-end security • Greater than 20% board savings compared to competing solutions that require two devices to deliver the same 1.6Tbp/s gearbox and hitless 2:1 mux modes • XpandIO enables port aggregation of low-rate Ethernet clients over higher speed Ethernet interfaces, optimised for enterprise platforms • ShiftIO feature combined with a highly configurable integrated crosspoint enables flexible connectivity between external switches, processors, and optics • Device variants with 48 or 32 Long Reach (LR) capable 112G PAM4 SerDes including programmability to optimize power vs. performance • Support for Ethernet, OTN, Fibre Channel and proprietary data rates for AI/ML applications “As the industry transitions to a 112Gbp/s PAM4 serial ecosystem for high-density routers and switches, line-rate encryption and efficient use of port capacity becomes increasingly important,” said Alan Weckel, Founder and Technology Analyst at 650 Group, LLC. Microchip and other OIF members will be showcasing how multi-vendor interoperability is accelerating industry solutions for the global network at the Congress Centre Basel.