Keysight delivers design-to-test workflow for high-speed digital designs

▤ Summary

In addition, lower voltages, higher currents, and requirements for equalisation within the DRAM receiver create signal integrity challenges that are difficult and costly to troubleshoot. Keysights PathWave ADS 2023 for HSD ensures rapid simulation setup and advanced measurements while providing designers insights to overcome signal integrity challenges. "Keysight has a long history of being on the forefront of channel simulation technology as well as test leadership in memory industry standards bodies including JEDEC," said Stephen Slater, Director of PathWave HSD Product Management at Keysight Technologies. "We are committed to building the widest portfolio of products and services for DDR enablement, including a complete design-to-test workflow for DDR5 memory from simulation to probing and fixturing. • Accurately predicts the closure and equalisation of the Data Eye: minimises impact of jitter, ISI and crosstalk using single-ended I/O (Input-Output) buffer information specification algorithmic modelling interface (IBIS-AMI) modelling with forwarded clocking, DDR bus simulation and accurate electromagnetic (EM) extraction of PCB signal routing • Shortens time-to-market with a single design environment that enables pathfinding in pre-silicon digital twins to address current integration requirements such as forwarded clocking and timing, IBIS algorithmic modelling interface (IBIS-AMI) modelling and compliance tests and future challenges like single-ended Pulse Amplitude Modulation 4 level (PAM4), for exploration of DDR6 • Rapidly generates buses via a parameterised pre-layout builder which enables designers to quickly generate wide buses of memory signals and create flexible schematics to explore trade-offs Automates design-to-test workflows with an easy connection between simulation and measurement domains to enable comparison of the stored data against measured results from physical prototypes.

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Keysight

$1B+