Cadence Joint Enterprise Data and AI platform accelerates AI-driven chip design development
Summary
Enabling a generational shift from single-run, single-engine algorithms in electronic design automation (EDA) to algorithms that leverage big data and artificial intelligence (AI) to optimise multiple runs of multiple engines across an entire SoC design and verification flow. The Cadence JedAI Platform enables engineers to glean actionable intelligence from massive volumes of chip design and verification data, opening the door to a new generation of AI-driven design and verification tools that dramatically improve productivity and power, performance, and area (PPA). Furthermore, the platform is cloud-enabled, offering highly scalable compute resources in a secure design environment from top cloud providers. “To enable the semiconductor industry to continue on its strong growth trajectory, it’s critical that the chip design process becomes much more efficient to keep pace with market demands,” said Pat Moorhead, CEO, Founder and Chief Analyst at Moor Insights & Strategy. “By using the Cadence JedAI Platform’s big data analytics, we can retrieve necessary information and solve bottleneck issues quickly.